(1) Field of the Invention
The present invention relates to a floating point type multiplier circuit and, more particularly, to a floating point type multiplier circuit to be used in a high speed digital signal processor which aims at real time access of data having a wide dynamic range (i.e., the maximum amplitude that can be taken by the data).
(2) Description of the Prior Art
A floating point type multiplier circuit is constructed of a fixed point multiplier for exclusive use of mantissa arithmetic and an adder for exclusive use of exponent arithmetic. Specifically, if two numbers to be multiplied are expressed by A.sub.1 =M.sub.1 .multidot.2.sup.e.sbsp.1 and A.sub.2 =M.sub.2 .multidot.2.sup.e.sbsp.2, the result of the multiplication is expressed by A.sub.0 =A.sub.1 .multidot.A.sub.2 =M.sub.1 .multidot.M.sub.2 .multidot.2.sup.e.sbsp.1.sup.+e.sbsp.2 so that the multiplication of M.sub.1 .multidot.M.sub.2 and the addition of e.sub.1 +e.sub.2 are performed. Here, M.sub.1 and M.sub.2 designate mantissas, and e.sub.1 and e.sub.2 designate exponents. In the multiplication of floating points, the mantissas of two inputs are so normalized as to maintain the effective length maximum. Specifically, "1" and "0" result in case the bit appearing next to the MSB (which is the abbreviation of "Most Significant Bit") is positive and and negative, respectively, and the point is located between the MSB and the second bit.
In case such multiplier is constructed of a digital circuit of binary number, the bit length of the mantissa and exponent is fixed for convenience of the circuit construction. Therefore, since the result of the multiplication, i.e., the product has to be expressed by a predetermined bit length, there arises a problem of "flow" (e.g., over-flow or under-flow).
In case the result of the multiplication is to be normalized, moreover, the mantissa is shifted so that the exponent has to be accordingly added and subtracted. If, in this case, the exponent fails to fall within the range expressed by a formal bit-length, the problem of the flow also results.
If the flow takes place in the mantissa and the exponent in that way, there has been adopted according to the prior art a method in which the flow is detected by flag and is compensated by a programming. As a result, it takes a considerable time to execute the program for compensating the over-flow, thus raising a defect that a high speed arithmetic cannot be accomplished. Especially in a real time access system, in which the input and output have to be processed with an identical time relationship, such as a communication equipment, a higher speed signal processor becomes necessary, and the speed-up of the multiplier especially taking the time is required.